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INTEGRATED CIRCUITS
DATA SHEET
SAA7219 MPEG2 Transport RISC processor
Product specification Supersedes data of 2000 Jun 14 File under Integrated Circuits, IC02 2001 Mar 28
Philips Semiconductors
Product specification
MPEG2 Transport RISC processor
CONTENTS 1 1.1 1.2 1.3 2.1 2.2 3 5 6 6.1 7 8.1 8.2 8.3 8.4 8.5 9 10 11 FEATURES External interfaces CPU related features MPEG2 systems features SAA7219 overview SAA7219 in a DVB system ORDERING INFORMATION PINNING APPLICATION INFORMATION Memory configurations PACKAGE OUTLINE Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS
SAA7219
2001 Mar 28
2
Philips Semiconductors
Product specification
MPEG2 Transport RISC processor
1 FEATURES
SAA7219
* Conditional access descrambling Digital Video Broadcasting (DVB) compliant and MULTI2 compliant * Stream demultiplexing: Transport Stream (TS), Packetized Elementary Stream (PES), program and proprietary streams * Internal 32-bit MIPS RISC based Central Processing Unit (CPU) supporting MIPS16 instruction set and running at 81 MHz * Low-power sleep modes supported across the chip * Comprehensive driver software and development tool support * Package: SQFP208. 1.1 External interfaces
* A General Purpose/High-Speed (GP/HS) interface supporting stream recording through IEEE 1394 interface IC * An extended JTAG interface for board test support. 1.2 CPU related features
The SAA7219 contains an embedded RISC CPU, which incorporates the following features: * A 32-bit PR3930 core running at 81 MHz * 8-kbyte, 2-way set associative instruction cache * 4-kbyte, 4-way set associative data cache * A programmable low-power mode, including wake-up on interrupt * A memory management unit with 32 odd/even entries and variable page sizes * Multiply/accumulate/divide unit with fast multiply/accumulate for 16-bit and 32-bit operands * Two fully independent 24-bit timers and one 24-bit timer including watchdog facilities * A real-time clock unit (active in Sleep mode) * Built-in software debug support unit as part of Extended Enhanced JTAG debug interface * On-chip SRAM of 4 kbytes for storing code which needs fast execution. 1.3 MPEG2 systems features
* Versatile compressed stream input at 108 Mbits/s * A 32-bit microcontroller extension bus supporting DRAM, SDRAM, Flash, (E)PROM and external memory mapped I/O devices. It also supports a synchronous interface to communicate with the integrated MPEG Audio Video Graphics Decoder (AVGD) SAA7215 at 40.5 Mbytes. * An IEEE 1284 interface (Centronics) supporting master and slave modes. Usable as a general purpose port. * An interface to IEEE 1394 devices (such as Philips PDI 1394 chip-set) * Two UART (RS232) data ports with Direct Memory Access (DMA) capabilities (187.5 kbits/s) including hardware flow control signals RXD, TXD, RTS and CTS for modem support * A Synchronous Serial Interface (SSI) to connect an off-chip modem analog front-end * An elementary UART with DMA capabilities, dedicated to front panel devices for instance * Two dedicated smart-card reader interfaces (ISO 7816 compatible) with DMA capabilities * Two I2C-bus master/slave transceivers with DMA capabilities, supporting the standard (100 kbit/s) and fast (400 kbits/s) I2C-bus modes * 32 general purpose, bidirectional I/O interface pins, 8 of which may also be used as interrupt inputs * One Pulse Width Modulated (PWM) output with 8-bit resolution
* Hardware based parsing of Transport Stream (TS), Philips Semiconductors program and proprietary software data streams. Maximum input rate is 108 Mbits/s. * A real-time descrambler consisting of 3 modules: - A control word bank containing 14 pairs (odd, even) of control words and a default control word - The DVB descrambler core implementing the stream decipher and block decipher algorithms - The MULTI2 descrambler algorithm implementing the CBC and OFB mode descrambling functions.
2001 Mar 28
3
Philips Semiconductors
Product specification
MPEG2 Transport RISC processor
* Hardware section filtering based on 32 different Packet Identifiers (PIDs) with a flexible number of filter conditions (8 or 4-byte condition plus 8 or 4-byte mask) per PID and a total filter capacity of 40 (8-byte condition checks) or up to 80 (4-byte condition checks) filter conditions: - 4 TS/PES filters for retrieval for data at TS or PES level for applications such as subtitling, TXT or retrieval of private data - Flexible DMA based storage of the 32 section substreams and 4 TS/PES data substreams in the external memory. * System time base management with a double counter mechanism for clock control and discontinuity handling, 2 Presentation Time Stamp (PTS)/Decoding Time Stamp (DTS) timers * A GP/HS filter which can serve as an alternate input from for example IEEE 1394 devices. The IEEE 1394 GP/HS mode supports packet insertion and has an internal SRAM for storing 2 packets. It can also output either scrambled or descrambled TS to IEEE 1394 devices. 2 2.1 GENERAL DESCRIPTION SAA7219 overview
SAA7219
The SAA7219 receives transport streams through a versatile stream input interface capable of handling both byte-parallel and bit-serial streams in various formats, supporting data streams up to and including 13.5 Mbyte/s (108 Mbits/s). The stream data is first applied to an on-chip descrambler incorporating a DVB descrambling algorithm, on the basis of 14 control word pairs stored in on-chip RAM. Demultiplexing is subsequently applied to the stream, to separate up to 32 individual data streams. The demultiplexer section includes clock recovery and timebase management. Program Specific Information (PSI), Service Information (SI), Conditional Access (CA) messages and private data are selected and stored in external memory, for subsequent off-line processing by the internal PR3930 CPU core. To support advanced board testing facilities the SAA7219 includes boundary scan test hardware, according to the EJTAG standard. The device features a low-power sleep mode, which is capable of sustaining set-top box standby functionality, thus eliminating the need for a separate front panel controller. The SAA7219 requires a supply voltage of 3.3 V and most devices input and output interfaces are 5 V tolerant except the extension bus which is 3.3 V only. The SAA7219 is mounted in a SQFP208 package. 2.2 SAA7219 in a DVB system
The device is part of a comprehensive source decoding kit which contains all the hardware and software required to receive and decode MPEG2 transport streams, including descrambling, demultiplexing. In addition, it includes a PR3930 core which is a 32-bit MIPS RISC-based CPU core supporting the MIPS 16 instruction set to reduce memory requirements and several peripheral interfaces such as UARTs, I2C-bus units, an IEC 1883, and an IEEE 1284 (Centronics) interface. The SAA7219 is therefore capable of performing all controller tasks in digital television receiver applications such as set-top boxes. Furthermore, the SAA7219 is compliant to DVB and MULTI2 standards. 3 ORDERING INFORMATION
The SAA7219 has been designed to offer optimum performance when used with the SAA7215 for MPEG2 AVG decoding. * Synchronous bus interface transfer at 40.5 MHz on 16 bits * SAA7215 has one dedicated SDRAM for MPEG2 audio video handling and one for graphics and CPU data. The second memory offers high bandwidth and low latency to the SAA7219 when accessing it to download graphics or executing some applications. This enables a high level of performance together with a low system cost by having one SDRAM for graphics and CPU data.
PACKAGE TYPE NUMBER NAME SAA7219HS/C2 SQFP208 DESCRIPTION plastic shrink quad flat package; 208 leads (lead length 1.3 mm); body 28 x 28 x 3.4 mm; high stand-off height VERSION SOT316-1
2001 Mar 28
4
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l pagewidth
2001 Mar 28
CPU section MIPS PR3930 CORE DATA CACHE INSTRUCTION CACHE TIMER 1 TIMER 2 TIMER 3 (WATCHDOG) DSU EJTAG MMU
4
Philips Semiconductors
MPEG2 Transport RISC processor
input stream output stream
BLOCK DIAGRAM
PWM
demultiplexer descrambler section
INPUT INTERFACE
PID FILTER
DESCRAMBLER DVB AND MULTI2 MPEG system-bus
AV FILTER
AUDIO AND VIDEO INTERFACE
AVD interface
GP/HS INTERFACE 1394 GATEWAY
PCR PROCESSING
TS/PES FILTERS
SECTION FILTERS
FILTER DMA CONTROLLER MPEG SYSTEM GATEWAY M MPEG SYSTEM INT.HANDLER Reset Clock PI-bus
5
S PI-BUS CTRL S EXTENSION BUS CONTROLLER M CARD READER 0 1 M UART 201 M SSI S PIO INTERFACE S I2C 0 1 M 1284 S RTC 32 kHz S INTERRUPT CONTROLLER S 4-KBYTE SRAM JTAG peripheral section
FCE374
JTAG interface
external bus interface
32-bit PIO smart card interface UART and SSI connections
SCL and 1284 bus SDA lines
Product specification
SAA7219
M = master peripheral with embedded DMA channel S = slave peripheral
Fig.1 Block diagram.
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MPEG2 Transport RISC processor
Table 1
SQFP208 package: 179 functional pins and 29 power supply pins SYMBOL PIN I/O BUFFER TYPE VOLT(1) DESCRIPTION
PIO interface (32 pins) PIO0 to PIO7 PIO8/BOOTIS32 PIO9/BOOTIS16 105 to 112 113 114 I/O I/O I/O bidirectional, 3 mA output drive 5 V bidirectional, 3 mA output drive 5 V bidirectional, 3 mA output drive 5 V usable as interrupt inputs and/or I/O lines PIO bit and PIO-strap. At power-on, it indicates the data bus size of the booting device. PIO bit and PIO-strap. At power-on, if BOOTIS32 is LOW, it indicates if the system should reboot from a 16-bit or 8-bit device. PIO bit and PIO-strap I/O lines or upper 16-bit data bus. The data bus width of the booting device is automatically configured at power-on.
PIO10 to PIO15 PIO(31:16)/D(31:16)
116 to 121
I/O
bidirectional, 3 mA output drive 5 V bidirectional, 6 mA output drive 5 V
2, 4 to 9, 11 to 16, I/O 18 to 20
Extension bus (58 pins) D15 to D0 21, 22, 24, 25, I/O 28 to 30, 33 to 36, 38 to 41 63 to 65, 67 to 71, O 73 to 77, 81 to 85, 87 to 90 49 48 46 43 44 42 62 47 50 to 56 58 59 60 O O O O O O O O O O I O bidirectional, 8 mA output drive 3.3 V lower 16-bit data bus
8 mA output drive
3.3 V
address bus
8 mA output drive 8 mA output drive 8 mA output drive 8 mA output drive 8 mA output drive 8 mA output drive 8 mA output drive 8 mA output drive 8 mA output drive 8 mA output drive TTL input 2 mA output drive
3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 5V 3.3 V
row access strobe for DRAM and SDRAM Bank 0 row access strobe for DRAM and SDRAM Bank 1 column access strobe lower byte column access strobe mid lower byte column access strobe mid upper byte column access strobe upper byte write enable chip select for SDRAM Bank 0 chip select Product specification
SAA7219
output enable Data termination acknowledge. Asserted LOW by the peripheral when the data bus is valid. selects the graphics SDRAM memory space of the SAA7215
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MPEG2 Transport RISC processor
UART 1 and SSI interfaces (5 pins) RXD1/V34_RXD TXD1/V34_TXD RTSN1/V34_FS 137 138 139 I O I/O TTL input 2 mA output drive 5V 3.3 V UART 1 receive data line or receive serial data of the SSI interface UART 1 transmit data line or transmit serial data of the SSI interface UART 1 request to send (output) or frame synchronization reference of the SSI interface (input) UART 1 clear to send or serial input interface clock of the SSI interface (up to 3.375 MHz) master clock for the SSI interface (36.684 MHz)
bidirectional, 3 mA output drive 5 V
CTSN1/V34_CLK MCLK UART 2 interface (2 pins) RXD2 TXD2
140 146
I O
TTL input 2 mA output drive
5V 3.3 V
135 136
I O
TTL input 2 mA output drive
5V 3.3 V
UART 2 receive data line UART 2 transmit data line
I2C-bus 0 interface (2 pins) SCL0 SDA0 149 150 I/O I/O bidirectional with open-drain 8 mA output drive bidirectional with open-drain 8 mA output drive 5V 5V I2C-bus 0 clock line I2C-bus 0 data line
Product specification
SAA7219
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MPEG2 Transport RISC processor
Smart card 0 interface (5 pins) CLK_CARD0 CMDVCCN0 RSTIN0 OFFN0 SC_I/O0 128 129 132 133 134 O O O I I/O 2 mA output drive 2 mA output drive 2 mA output drive TTL input bidirectional with open-drain 8 mA output drive 3.3 V 3.3 V 3.3 V 5V 5V ISO UART 0 card clock ISO UART 0 command of the VCC ISO UART 0 reset of the card ISO UART 0 card presence ISO UART 0 I/O line
Smart card 1 interface (5 pins) CLK_CARD1 CMDVCCN1 RSTIN1 OFFN1 SC_I/O1 122 123 124 125 126 O O O I I/O 2 mA output drive 2 mA output drive 2 mA output drive TTL input bidirectional with open-drain 8 mA output drive 3.3 V 3.3 V 3.3 V 5V 5V ISO UART 1 card clock ISO UART 1 command of the VCC ISO UART 1 reset of the card ISO UART 1 card presence ISO UART 1 I/O line
Input Stream interface (11 pins) PKTSTROBE PKTSYNC PKTVALID GP/HS interface (11 pins) GPDATA7 to GPDATA0 GPVALID GPSYNC GPSTROBE 166 to 169, 171 to 174 175 176 177 I/O I/O I/O I/O bidirectional, 3 mA output drive 5 V bidirectional, 3 mA output drive 5 V bidirectional, 3 mA output drive 5 V bidirectional, 3 mA output drive 5 V GP/HS data bus Product specification GP/HS control lines GP/HS control lines GP/HS control lines 154 155 156 I I I I TTL input TTL input TTL input TTL input 5V 5V 5V 5V byte strobe or bit strobe packet synchronization data valid, or bit stream word select 8-bit primary TS data input
PKTDATA7 to PKTDATA0 157 to 164
SAA7219
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MPEG2 Transport RISC processor
SAA7215 MPEG interface (11 pins) V_STROBE A_STROBE AV_ERROR AV_DATA7 to AV_DATA0 93 94 95 96 to 103 O O O O 2 mA output drive 2 mA output drive 2 mA output drive 2 mA output drive 3.3 V 3.3 V 3.3 V 3.3 V HIGH-to-LOW transition strobes the video data in the AV_DATA stream HIGH-to-LOW transition strobes the audio data in the AV_DATA stream flag for bit stream error (active HIGH) MPEG audio/video stream output port
IEEE 1284 interface (18 pins) GPD0 to GPD7 NSELECTIN NINIT NSTROBE NACK BUSY PERROR SELECT NAUTOF NFAULT DIR1284 PWM interface (1 pin) PWM0 System interface (3 pins) RESETN 1 I/O bidirectional with open-drain 8 mA output drive and Schmitt trigger input with high hysteresis 3.3 V General system reset; active LOW. The pad is bidirectional with an open-drain which is asserted LOW when the internal watchdog time out is detected. 13.5 MHz crystal input 13.5 MHz crystal output 165 O open-drain 8 mA output drive 5V open-drain 5 V tolerant for VCXO control 190 to 197 199 200 201 202 203 204 205 206 207 208 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O bidirectional, 3 mA output drive 5 V bidirectional, 3 mA output drive 5 V bidirectional, 3 mA output drive 5 V bidirectional, 3 mA output drive 5 V bidirectional, 3 mA output drive 5 V bidirectional, 3 mA output drive 5 V bidirectional, 3 mA output drive 5 V bidirectional, 3 mA output drive 5 V bidirectional, 3 mA output drive 5 V bidirectional, 3 mA output drive 5 V 2 mA output drive 3.3 V parallel data bus host to peripheral select line host to peripheral control line host to peripheral strobe line peripheral acknowledge line peripheral busy line peripheral error line peripheral on-line host to peripheral control line peripheral error line direction control of the external buffers
XTAL1 XTAL2
153 152
I O
3.3 V 3.3 V
Product specification
SAA7219
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MPEG2 Transport RISC processor SAA7219
Product specification
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208
handbook, halfpage
Philips Semiconductors
SYMBOL Supplies (29 pins) VDD(P)
PIN
I/O - -
BUFFER TYPE
VOLT(1) -
DESCRIPTION
MPEG2 Transport RISC processor
3, 17, 31, 43, 66, 80, 92, 115, 145 and 187
pad supply voltage
VSS(P)
10, 23, 37, 57, 72, - 86, 104, 127, 170 and 198 27, 79, 130 and 182 26, 78, 131 and 183 151 - - -
-
-
ground supply
VDD(C) VSS(C) VDD(PLL) Note
- - -
- - -
core supply voltage ground supply analog supply for the on-chip PLLs
1. 5 V tolerant inputs can receive signals swinging between VSS and 3.3 V or VSS and 5 V. 5 V tolerant bidirectional I/O pins can receive signals swinging between VSS and 3.3 V or VSS and 5 V when they are inputs and swing between VSS and VDD when they are outputs.
157
1
156
SAA7219
52
105
53
104
Product specification
FCE380
SAA7219
Fig.2 Pin configuration
Philips Semiconductors
Product specification
MPEG2 Transport RISC processor
6 APPLICATION INFORMATION
SAA7219
handbook, full pagewidth
RF in
TDA8060 TDA5056 TUNER 2 SAA8044 (SDD) I2C-bus FRONT PANEL CONTROL VXX MODEM MPEG TS BUFFERS IEEE 1394 L + PHY IEEE 1384 RS232 IEEE 1394
Telecommunication i/f
SAA7219
Smart cards
TDA8004 AV PES 16-MBIT SDRAM
FLASH
DRAM (OPTIONAL)
FCE375
SAA7215
16-MBIT SDRAM (OPTIONAL) CVBS/YC LR A DAC RGB
SWITCHING
SCART1 SCART2 SCART3
Fig.3 Set-top box example.
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Philips Semiconductors
Product specification
MPEG2 Transport RISC processor
6.1 Memory configurations Low-end and high-end memory configurations SDRAM 1M x 16 DRAM 256K x 16 PROM 512K x 8
SAA7219
Table 2
CONFIGURATION Low-end High-end
FLASH PERIPHERALS -
up to 2 banks of 64 Mbits up to 2 banks of 4 Mbytes up to 4 Mbytes 2 to 7 banks of up to 4 Mbytes
16
DRAM/ SDRAM
8 PROM FLASH RESERVED
SAA7219
16 16 SDRAM (MPEG)
FCE376
SAA7215
Fig.4 Typical low-end memory configuration.
32 DRAM PROM FLASH 1 FLASH 2
SAA7219
16
16
SDRAM (MPEG) SDRAM GRAPHICS
SAA7215
16
FCE377
Fig.5 Typical high-end unified memory configuration.
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Philips Semiconductors
Product specification
MPEG2 Transport RISC processor
7 PACKAGE OUTLINE
SAA7219
SQFP208: plastic shrink quad flat package; 208 leads (lead length 1.3 mm); body 28 x 28 x 3.4 mm; high stand-off height
SOT316-1
c
y
X
A
156 157 105 104
ZE
e E HE A2 A1 (A 3) Lp L pin 1 index
208 53 52
A
wM bp
detail X
1
e
bp D HD
wM
ZD B
vM A
vM B
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 4.10 A1 0.50 0.25 A2 3.6 3.2 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 28.1 27.9 E (1) 28.1 27.9 e 0.5 HD 30.9 30.3 HE 30.9 30.3 L 1.3 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 Z D (1) Z E (1) 1.39 1.11 1.39 1.11 8 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT316-1 REFERENCES IEC JEDEC MS-029 EIAJ EUROPEAN PROJECTION
ISSUE DATE 99-12-27 00-01-25
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Philips Semiconductors
Product specification
MPEG2 Transport RISC processor
8 8.1 SOLDERING Introduction to soldering surface mount packages
SAA7219
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 8.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. 8.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. 8.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Product specification
MPEG2 Transport RISC processor
8.5 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable suitable suitable suitable suitable suitable
SAA7219
REFLOW(1)
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
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Philips Semiconductors
Product specification
MPEG2 Transport RISC processor
9 DATA SHEET STATUS PRODUCT STATUS(2) Development DEFINITIONS
SAA7219
DATA SHEET STATUS(1) Objective data
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Preliminary data
Qualification
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 10 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 11 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. ICs with MPEG-2 functionality Use of this product in any manner that complies with the MPEG-2 Standard is expressly prohibited without a license under applicable patents in the MPEG-2 patent portfolio, which license is available from MPEG LA, L.L.C., 250 Steele Street, Suite 300, Denver, Colorado 80206.
2001 Mar 28
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Philips Semiconductors
Product specification
MPEG2 Transport RISC processor
12 PURCHASE OF PHILIPS I2C COMPONENTS
SAA7219
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
2001 Mar 28
18
Philips Semiconductors
Product specification
MPEG2 Transport RISC processor
NOTES
SAA7219
2001 Mar 28
19
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2001
Internet: http://www.semiconductors.philips.com
SCA 72
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753504/03/pp20
Date of release: 2001
Mar 28
Document order number:
9397 750 08175

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